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Design Verification Engineer – SystemVerilog/UVM
ACCELRlinkedin.com
Sep 18, 20265w ago
Full-timeColomboHardware
About the role
The Design Verification Engineer will join an ASIC design verification team, focusing on front-end verification of complex digital IPs for advanced ASIC/SoC designs at a leading global semiconductor company. The role involves developing SystemVerilog/UVM testbenches, creating and executing verification plans, developing testcases, running RTL simulations and regressions, debugging functional issues, and driving coverage closure. The engineer will work closely with RTL designers and participate in verification reviews and milestone deliveries.
Must have
- Strong hands-on experience with SystemVerilog and UVM
- Good understanding of digital design and RTL concepts
- Experience with RTL simulation and debugging
- Knowledge of functional coverage and constrained-random verification
- Good analytical and problem-solving skills
Nice to have
- Experience in ASIC/SoC Design Verification
- Exposure to Synopsys simulation tools
- Basic scripting (Python, Perl, or Shell)
Technologies
- ASIC
- Bash
- Perl
- Python
- SystemVerilog
- UVM
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