Design Verification Engineer – SystemVerilog/UVM

About the role

The Design Verification Engineer will join an ASIC design verification team, focusing on front-end design verification of complex digital IPs for advanced ASIC/SoC designs. The role involves developing SystemVerilog/UVM testbenches, creating and executing verification plans, developing testcases, running RTL simulations and regressions, debugging functional issues, analyzing coverage, and collaborating with RTL designers. The position is with a team working on cutting-edge ASIC/IP development for a leading global semiconductor company.